In current mode logic (CML) circuits, voltages are typically referenced from the most positive supply voltage. However, an analog circuit connected to such a digital CML circuit may need to have its threshold voltages referenced to the negative supply. As a result, at the digital/analog interface, there is a need for a circuit which shifts the signal level between the two voltage supply rails.
JP-A-5-315936 discloses a level shifting circuit in which an input signal is applied to the base of a first NPN transistor. The emitter of this first transistor is connected to the collector terminal of a second NPN transistor and also, through a resistor, to the base of the second NPN transistor the base of this second transistor is connected to ground through a first current source circuit, while the emitter terminal of this second transistor is connected to ground through a second current source circuit, and the emitter terminal of the second transistor also acts as the circuit output.
JP-A-6-260925 discloses a further level shift circuit, in which first and second input terminals, for receiving a differential input voltage, are connected to the bases of first and second NPN transistors. The collector terminals of these transistors are connected together, and the emitter terminals are connected to respective output terminals which receive a differential output voltage. The emitters of these transistors are further connected through respective resistors to respective halves of a current mirror circuit.
An object of the present invention is to provide a level shifting circuit which, in preferred embodiments, can maintain a differential signal gain of unity, and, again in preferred embodiments, can provide a fixed output common mode level which is independent of the supply voltage and the input common mode voltage.